Taeyoon Kim1 2 Jung Wook Lim1 2 Seong Hyun Lee1 Jeho Na1 Jiwoon Jeong1 Kwang Hoon Jung1 2 Gayoung Kim1 2 Sun Jin Yun1 2

1, ICT Materials Research Group, Materials & Components Basic Research Division, Electronics and Telecommunications Research Institute, Daejeon, , Korea (the Republic of)
2, Advanced Device Engineering, University of Science and Technology, Daejeon, , Korea (the Republic of)

Recently, oxide-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have been actively studied for the applications of non-volatile memory devices in transparent and flexible electronic products. Oxide-MOSFETs have much lower off-state leakage current than Si-MOSFETs, allowing low-power memory operation, and further advantages such as good uniformity, low process temperature, and high transmittance in the visible wavelength range. Conventional oxide-based non-volatile memory generally uses positive and negative gate voltage (VG) pulses to achieve the program and erase states, respectively. However, the n-type nature of most oxide semiconductors makes it difficult to conduct sufficient amounts of holes in the channel oxides, leading to a high power consumption and long erase times; thus input power sources (e.g. light) in addition to voltage are required. In a memory device, the difference between the programming and erasing voltages is known as the “memory window”. In a non-volatile memory, the memory window should be set to secure a sufficient margin of read voltage (Vread) for stable device operation; wider memory windows can be achieved with more defect sites trapping more charges. However, shallow traps among the defect sites adversely affect device stability. Therefore, it is necessary to selectively exclude shallow trap sites to satisfy both a wide memory window and high device stability.
In this work, we propose TiO2 MOSFET-based non-volatile memory device, employing the deep trap interface (DI) sites as a simple floating gate without tunneling oxide. For the fabrication of TiO2 MOSFET, 80 nm-thick Al2O3 gate dielectric layerand 30 nm-thick TiO2 films were deposited by plasma enhanced atomic layer deposition on a n+ Si wafer which plays a role of back gate. In order to demonstrate performance of TiO2 MOSFET, we measured electrical characteristics of the fabricated devices in the dark and violet light (VL)-irradiated conditions at 25 °C. For VL irradiation, we used standard LEDs (center wavelength of 400 nm) as a light source with an incident power of 0.13 W/cm2. This device demonstrated a high on/off ratio of 107 and a sizable memory window due to deep traps at the interface between Al2O3 and TiO2. Interestingly, irradiation with 400 nm VL could completely restore the program state to the initial state (performing an erasing process) owing to the visible light-sensitive TiO2 channel. Device reproducibility was greatly enhanced by selectively passivating shallow traps using an in-situ H2-plasma treatment. The passivated memory device showed a highly reproducible memory window and on-state current even during a retention bake test at 85 °C. We expect that our simple-structured TiO2-based non-volatile memory device, which is completely erasable only by light irradiation and shows reproducible and stable operation, will usefully employed in a wide range of future electronic devices.